Memory devices are structured to have one or more arrays of memory cells that are arranged, at least logically, in rows and columns. Each memory cell stores data as an electrical charge that is accessed by a digit line associated with the memory cell. A charged memory cell, when the memory cell is accessed, causes a positive change in voltage on the associated digit line with respect to a precharge voltage, and an accessed memory cell that is not charged causes a negative change in voltage on the associated digit line with respect to the precharge voltage. The change in voltage on the digit line may be sensed and amplified by a sense amplifier to indicate the value of the data state stored in the memory cell.
Conventional sense amplifiers are typically coupled to a pair of complementary digit lines to which a large number of memory cells (not shown) are connected. FIG. 1 is a circuit diagram of a conventional sense amplifier circuit and a pair of complementary digit lines. As known in the art, when memory cells are accessed, a row of memory cells are activated and sense amplifiers are used to amplify a data state for the respective column of activated memory cells by coupling each of the digit lines of the selected column to voltage supplies such that the digit lines have complementary logic levels.
When a memory cell is accessed, the voltage of one of the digit lines increases or decreases slightly, depending on whether the memory cell coupled to the digit line is charged or not, resulting in a voltage difference between the digit lines. While the voltage of one digit line increases or decreases slightly, the other digit line does not and serves as a reference for the sensing operation. Respective transistors are enabled due to the voltage difference, thereby coupling the slightly higher voltage digit line to a supply voltage and the other digit line to a reference voltage, such as ground to further drive each of the digit lines in opposite directions and amplify the selected digit line signal.
The digit lines are precharged during a precharge period to a precharge voltage, such as one-half of a supply voltage, so that a voltage difference can be accurately sensed and amplified on sense nodes during a subsequent sensing operation. However, when a low data state signal from, a memory cell is weakly signaled, while P-channel transistors of a sense amplifier has a weakness to voltage threshold (Vt) offset, the digit lines may not be amplified to reflect a logic high or low level in a timely fashion, and sensed and amplified levels on sense nodes may not be reflected on local input/output (LIO) nodes while the LIO nodes are coupled to the sense nodes. Such delay in amplification can cause the sense amplifier to erroneously to provide signals in the wrong direction. There is, therefore, a need for a sense amplifier design that timely amplifies the digit lines even for the weak low data state signal from the memory cell.